1. Field of the Invention
This invention is related to translation lookaside buffers (TLBs) and minimizing the size of TLB comparisons.
2. Description of the Related Art
Processors and computer systems that include the processors typically implement a virtual memory system, in which most software executing on the processors and accessing memory do so using virtual (or effective) addresses. These addresses are translated through the virtual memory system to physical addresses, which are used to access memory.
Performing a translation frequently requires several accesses to page tables in memory. Accordingly, most processors implement a cache for a subset of the translations from the page tables, referred to as a translation lookaside buffer (TLB). The TLB caches the results of the translation process, which includes an identification of the virtual address and the corresponding physical address. The data cached in the TLB and used to translate a given range of virtual addresses (e.g., a page) is referred to as a “translation” for the range/page.
To distinguish between translations, the TLB can contain one or more comparison fields. One such field is commonly referred to as a “virtual page number”; collectively, the comparison fields are referred to as a “tag.” As the number of address bits in the virtual address space or tag space increases, the width of the comparison increases as well, which increases the latency of the TLB.